TSMC touts advanced packaging, 2nm progress at tech symposium

Taipei, May 14 (CNA) Taiwan Semiconductor Manufacturing Co. (TSMC) showcased advances in its next-generation chipmaking and packaging technologies Thursday at the 2026 Taiwan Technology Symposium in Hsinchu.

Company executives unveiled the new A13, A12, and N2U process technologies while announcing mass production this year of what it described as the world's largest chip-on-wafer-on-substrate (CoWoS) packaging solution.

Yuan Li-pen (袁立本), TSMC's vice president for business development, said the 5.5-reticle-size CoWoS technology has achieved yields exceeding 98 percent.

The announcement came amid recent reports of advances by Intel and Samsung in advanced packaging and foundry technologies.

Intel's EMIB-T packaging technology was reported to have achieved yields of about 90 percent, while Samsung's 2-nanometer (2nm) process yields reportedly reached the mid-50-percent range.

Looking toward future high-performance computing needs, Yuan said TSMC expects to begin production in 2028 of a 14-reticle-size CoWoS platform capable of integrating 20 high-bandwidth memory (HBM) chips. A larger version capable of integrating 24 HBM chips is slated for 2029.

The A13 and A12 processes are also scheduled for mass production in 2029, Yuan added.

Meanwhile, B.Z. Tien (田博仁), TSMC vice president for operations and advanced technology engineering, said the A16 process remains on track for production in the second half of 2026.

To meet surging demand for AI and 2nm chips, Tien said TSMC plans to launch five new fabs in 2026.

The company projects a compound annual growth rate of 70 percent for 2nm capacity from 2026 to 2028, with CoWoS and SoIC advanced packaging capacity expected to grow at an annual rate of more than 80 percent through 2027, he added.

According to Yuan, TSMC has already received about 25 finalized 2nm chip designs, with more than 70 additional customer projects currently in development.