TSMC unveils A13 process at North American forum

Taipei, April 23 (CNA) Taiwan Semiconductor Manufacturing Co. (TSMC) on Wednesday unveiled its next-generation A13 process at its North America Technology Symposium in California, saying that it was targeting volume production in 2029.

The new A13 process is aimed at meeting growing demand for artificial intelligence (AI), high-performance computing (HPC), and mobile applications, said TSMC, the world's largest contract chipmaker.

TSMC was showcasing its latest technologies and services at its largest annual customer forum, which was held Wednesday in Santa Clara, California under the theme "Expanding AI with Leadership Silicon."

In a statement Wednesday, TSMC Chairman and CEO C.C. Wei (魏哲家) said that customers expect advanced nodes like the A13 to be ready for volume production when next-generation designs require them, adding the company continues to lead in chip density, performance and power efficiency.

According to TSMC, the A13 improves on A14 by shrinking the chip area by 6 percent while maintaining full design-rule compatibility, enabling rapid migration to nanosheet transistor technology. Additional gains in performance and power efficiency are achieved through design-technology co-optimization, the company said.

At the symposium, TSMC also previewed its A12 process, featuring a "super power rail" architecture to provide backside power delivery for AI and HPC applications, with production slated for 2029.

In its 2-nanometer platform, N2U will deliver a 3-4 percent speed increase, or 8-10 percent lower power use, compared with the N2P, with production expected in 2028, the company said.

On advanced packaging, TSMC said it is expanding CoWoS technology from 5.5 times reticle size to 14 times, capable of integrating about 10 compute dies and 20 high-bandwidth memory (HBM) stacks, with production planned for 2028. Larger CoWoS and wafer-scale SoW-X are targeted for 2029.

The company said it is also advancing SoIC 3D stacking, including A14-to-A14 by 2029, offering 1.8 times the I/O (input/output) density of 2nm-based SoIC.

Its COUPE photonics engine is set to reach a key milestone, with co-packaged optics entering production in 2026, doubling power efficiency and cutting latency by 90 percent, it said.

For automotive and edge AI, TSMC introduced N2A, its first nanosheet-based automotive node, saying AEC-Q100 certification is expected in 2028.