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Equipment installation begins at TSMC's 2nm Kaohsiung fab

11/26/2024 12:05 PM
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Construction progress of TSMC's Kaohsiung plant in the Nanzih Industrial Park as of March. CNA file photo
Construction progress of TSMC's Kaohsiung plant in the Nanzih Industrial Park as of March. CNA file photo

Taipei, Nov. 26 (CNA) Taiwan Semiconductor Manufacturing Co. (TSMC) began installing equipment at its 2-nanometer fab in Kaohsiung, paving the way for a trial run at the company's second plant featuring it most advanced technology in the first half of 2025.

TSMC confirmed on Tuesday that it had begun moving equipment into the Kaohsiung facility but remained low key, saying it was simply an internal event.

Local news media reported, however, that a ceremony was held to mark the occasion, attended by TSMC Executive Vice President and Co-Chief Operating Officer Y.P. Chyn (秦永沛), Kaohsiung Mayor Chen Chi-mai (陳其邁), and representatives of the chipmaker's suppliers.

TSMC is building up its 2nm production capacity in Hsinchu in northern Taiwan and Kaohsiung in southern Taiwan. The 2nm process is more sophisticated than the 3nm process, TSMC's most advanced technology currently in mass production.

At an investor conference in mid-October, TSMC Chairman C.C. Wei (魏哲家) said the company's clients appeared more interested in its 2nm process than the 3nm process and was therefore preparing more 2nm production capacity to meet demand.

TSMC already has a 2nm wafer plant where a trial run has begun, located in Baoshan in Hsinchu County. Mass production at that facility is expected to begin in 2025.

A second plant is under construction in Baoshan, with commercial production set for 2026.

In Kaohsiung, the first 2nm plant is scheduled to start mass production in 2026, and a second one is under construction. TSMC has said it will build a third fab in Kaohsiung to roll out chips made on high-end processes but did not specify the technologies.

The 2nm process will be 10-15 percent faster compared to the current N3E, an enhanced version of the 3nm process, and consume less power. In addition, densities will also be higher by more than 15 percent.

TSMC is also developing the A16 process, an upgraded version of the 2nm process.

The company describes it as a next-generation nanosheet-based technology featuring Super Power Rail, "an innovative, best-in-class backside power delivery solution" that "improves logic density and performance by dedicating front-side routing resource to signals."

(By Chang Chien-chung and Frances Huang)

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