TSMC's development of 3nm process ahead of schedule: chairman
Taipei, Feb. 19 (CNA) The development of the advanced 3 nanometer process by Taiwan Semiconductor Manufacturing Co. (TSMC), the world's largest contract chipmaker, is ahead of schedule, according to company chairman Mark Liu (劉德音).
Liu gave the update in an online speech at the International Solid-State Circuits Conference (ISSCC) earlier this week, but he did not provide any details about how far along or ahead of schedule the process is.
Before Liu spoke, TSMC had said trial production of 3nm chips is scheduled for later this year in a wafer fab located in the Southern Taiwan Science Park in Tainan, and commercial production is expected to begin in the second half of 2022.
Liu said TSMC's 3nm technology is adopting the FinField-effect-transistor (FInFeT) process.
FinFET is a 3D transistor structure that allows a chip to run faster than previously possible on the same amount of power or to run at the same speed on reduced power.
According to the company, the logic density of the 3nm process will be 75 percent higher than that of the 5nm process, currently TSMC's most advanced process being produced commercially.
In addition, the 3nm process is expected to be 15 percent more efficient than the 5nm process and cut power consumption by 30 percent, according to TSMC.
After the 3nm process, Liu said, TSMC is developing the more sophisticated 2nm process, which will use the Gate-all-around (GAA) application, a technology that allows transistors to get around the size limitations of FinFETs as they reach the 5nm and 3nm levels.
TSMC has announced it will build a wafer plant in Hsinchu to roll out chips made using the 2nm process, but the company has yet to release an exact timetable for the development of the 2nm process.
The ISSCC 2021, the foremost global forum for the presentation of advances in solid-state circuits and systems-on-a-chip, kicked off on Feb. 13 and runs through Feb. 22.
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