TSMC to start construction of 4th, 5th fabs in Kaohsiung next year

Taipei, Dec. 28 (CNA) Taiwan Semiconductor Manufacturing Co. (TSMC), the world's largest contract chipmaker, plans to begin construction of its 4th and 5th wafer fabs in the southern Taiwanese city Kaohsiung next year, targeting development of high-end processes.

The two facilities -- P4 and P5 -- are part of TSMC's production expansion program which aims to build five fabs in Kaohsiung.

Arthur Chuang (莊子壽), the chipmaker's vice president for the facility division, said on Thursday that the five facilities are expected to create 8,000 jobs.

To respond to the fast-changing global semiconductor industry and escalating international competition, TSMC said the company has to keep growing by expanding its production footprints.

The P4 and P5 fabs will be located next to the third fab or P3 and its construction is scheduled to be completed in 2027.

Speaking with residents of Kaohsiung who are concerned about the environmental impact resulting from the fab construction, Chuang said TSMC completely abides by the law and the construction plan is proceeding as scheduled.

According to TSMC, its first fab in Kaohsiung or P1, which has started equipment installation, is scheduled to start mass commercial production of the advanced 2 nanometer process in 2025. The 2nm process will become the latest technology for TSMC to begin mass production after launching commercial production of the 3nm process at the end 2022.

The 2nm process will be 10-15 percent faster compared to the current N3E, an enhanced version of the 3nm process, and consume less power. In addition, densities will also be higher by more than 15 percent.

Construction of TSMC's second fab, or P2, is set to be completed next year, also using the 2nm process, while construction of the chipmaker's third fab is expected to be completed in 2026. That fab will use the 2nm process or more sophisticated technologies.

TSMC did not disclose what process the 4th and 5th fabs will use.

At an investor conference in mid-October, TSMC Chairman C.C. Wei (魏哲家) said the company's clients appeared more interested in its 2nm process than the 3nm process and the company was therefore preparing more 2nm production capacity to meet demand.

TSMC already has a 2nm wafer plant where a trial run has begun, located in Baoshan in Hsinchu County. Mass production at that facility is expected to begin in 2025.

Next to the 2nm technology, TSMC is developing the A16 process mass production which is scheduled in the first half of 2026. The company describes it as a next-generation nanosheet-based technology featuring Super Power Rail, "an innovative, best-in-class backside power delivery solution" that "improves logic density and performance by dedicating front-side routing resource to signals."